A computer system may include a chip adapted to receive data and/or transmit data via a link. The computer system may include logic (hereinafter “error detection and recovery logic”) adapted to detect one or more errors in the received data and enable the system to recover from such errors. To test the error detection and recovery logic, one or more errors may intentionally be injected into the data. In a conventional computer system, such errors may be inserted in the data by physically breaking the link and applying the errors to the link. However, such a method of injecting errors in data may not be acceptable for a computer system employing a high-speed link. Accordingly, improved methods and apparatus for error injection are desired.